Abstract: A small transition delays and little faults create major concern in digital circuits. It Produce greater impact on not only for simple memory but also for most of the memory applications. During encoding and decoding process, the error may occur in the codeword which results in the mismatching or loss of information. Error detection and correction are main issues in the memory which needs to be identified and corrected. The proposed method will identify the error and correct the error in the memory application using Majority Logic Decoder and Detector (MLDD). MLDD corrects the error based on number of parity check equation. This technology reduces the N-iteration to three iteration, if the codeword doesn’t contain any fault. It reduces the memory access time when there is no fault in data read. However it reduces the decoding time that increase memory application. Therefore delay is reduced. All the codes for MLDD design are written in VHDL. Modelsim SE 6.3f used for simulation process and the system is implemented on Sparatan-6 - XC6SLX16 - CSG324C FPGA kit.
Keywords: Encode, Error correction, Fault detection, Serial one step MLD, Majority logic decoder/detector, Memory, Soft error, sorting network