Abstract: Static random-access memory (SRAM) is a type of semiconductor memory that uses bistable latching circuitry to store each bit. The term static differentiates it from dynamic RAM (DRAM) which must be periodically refreshed. SRAM exhibits data remanence but it is still volatile in the conventional sense that data are eventually lost when the memory is not powered. In this paper, a new 8T SRAM cell, which employs a single bitline scheme to perform the write and read operations, is proposed. This scheme enhances the write ability and read stability by cutting off the feedback loop of the inverter pair, thereby eliminating the read and write constraints on the transistor dimensions. SRAM based structures within the processor are especially liable to NBTI as one of the PMOS devices in the memory cell always has an input 0. So in order to reduce the power consumption, an inverter is connected to the other end of NMOS device, such that the inverter replaces the ground. Now the size may be somewhat increased but the power leakage is controlled by the use of the inverter.