Abstract: Duty-cycle correctors are widely used in high-speed devices and system-on-a-chip applications. Because both the positive and negative edges of the clock are utilized for sampling the input data, these systems require an exact 50% duty cycle of the input clock. However, as the clock signal is distributed over the entire chip with clock buffers, the duty cycle of the clock is often far from 50%. Because of the unbalanced rise and fall times, as a result of variations in process, voltage, and temperature. To resolve this problem and to correct the duty-cycle error many approaches are presented. In this work, wide-range NAND gate based glitch-free all-digital duty-cycle corrector is presented. The proposed NAND gate based glitch-free ADDCC not only achieves the desired output/input phase alignment, but also maintains the output duty cycle at 50% with a short locking time. In addition, the proposed method can mitigate the delay mismatch problem and produce minimum delay without any glitch. The circuit complexity also is reduced in the proposed NAND gate based ADDCC. The simulation is carried out in 0.65 nanometer CMOS process. An experimental result shows that the power consumed, delay and area is reduced in the proposed architecture. Simulation results are obtained using MODELSIM 6.3f. The power, area and delay are obtained using the XILINX ISE 8.1 software.
Keywords: All-Digital Duty-cycle corrector (ADDCC), half-cycle delay line, High resolution, Phase alignment.