Abstract: An arbitrary design implemented into a field-programmable gate array (FPGA). FPGA contains many logical blocks. Fault equivalence and fault dominance method are used to detect the fault with minimum time period. An approach provides transparent scan to share tests among different logic blocks whose primary inputs and outputs are included in scan chains even if the blocks have different numbers of state variables. The transparent-scan sequences based on tests for one logic block could detect faults in other logic blocks, with different numbers of state variable. It uses n number of test configuration instead of 2n number of test configuration by test code algorithm. Transparent scan enhances the ability to produce a compact test set for a group of logic blocks. The procedure obtains a set of transparent-scan sequences for a group of logic blocks from compacted test sets for the logic blocks in the group. From this set, it chooses a subset that finds all the target faults, which are propagated by the complete set by using Modelsim and area is obtained by using the XILINX ISE 8.1 software.
Keywords: Full-scan circuits, test compaction, test generation, transparent scan, Field-programmable gate array (FPGA) testing.