Abstract: Multiplexer can be designed using Adiabatic array logic, CMOS logic, pass transistor logic. This paper describes a multiplexer using adiabatic logic. The Adiabatic logic are low power circuits which are reversible logic to conserve energy, it brings about a great deal of power minimization in digital circuits. The proposed circuits show lesser power dissipation then the conventional static CMOS logic style. All the designs were simulated using Tanner EDA tool v15.0. Simulations were done at 90nm technologies.

Keywords: Adiabatic logic, power dissipation, power saving, Tanner EDA tool v15.0.