Abstract: Clock Recovery circuits are used to detect the transition in the received data and generate a periodic recovered clock. These circuits are used in high speed asynchronous communication systems. This paper presents the design of clock recovery circuit using analog pll in 45nm technology. The proposed circuit is designed keeping in mind some basic design goals which are nothing but the expected enhancement in those parameters which reflects the performance and robustness of the circuit. Such as- To shift the frequency from 2Ghz to 3Ghz, increase rise time by 20%, increase the data rate by 25%, To overcome drawbacks of earlier models, to maintain robustness of circuit, reduce area, To build a power efficient circuit. The proposed circuit consist of TSPC-DFF based phase frequency detector/XOR frequency detector, single ended/differential wide swing charge pump, ring VCO, low pass filter, TSPC based frequency divider(DFF based) .

Keywords: Clock recovery circuit, PLL, Phase Frequency detector, VCO, Charge Pump, Frequency Divider.