Abstract: A 4-bit pipeline Analog-to-digital Converter (ADC) is designed using switched capacitor circuit. ADC is designed in 3 stages, 1.5 bit/stage pipeline is used in first two stages and third stage uses two bit flash ADC. The ADC is designed on 0.25 Ám CMOS technology at 2.5 V supply voltage in Tanner EDA tool. S/H is used in first stages that consume most of the power consumed by the ADC, after first stage S/H circuit is removed, and also the scaling is used to reduce the power consumption. Cascodeopamp is designed with gain of 72.52 dB, phase margin of 66║ and unity gain bandwidth of 162.61MHz. The ADC is designed at sampling rate of 5 MS/s and consumes 158.1208 mW powers.
Keywords: Analog-to-digital conversion (ADC), capacitor sharing, opamp sharing, switched capacitor, pipeline ADC, Non overlapping clock.