Analysis, Design and implementation of Low Power and delay of 10T Full adder at Different technology

Abstract: Power consumption has emerged as a primary design constraint for today VLSI integrated circuits (ICs). AS per reducing Technology, mostly Nanometre technology regime, leakage power has become a major component of total power. Full adder is the heart of any central processing unit that is a core component employed in all the processors. Full adder is the basic functional unit of an ALU. The power consumption of a processor is lowered by lowering the power consumption of an ALU. In this paper we introduced low power consume & Propagation Delay of one-bit full adders by using 10T. The analysis of the developed full adder design is done at room temperature CMOS 45nm,90nm and 180nm technologies using Cadence virtuoso tool. The result shows the comparison between different CMOS technologies in 45nm,90nm and180nm using Cadence virtuoso tool on the design in regards of power dissipation, propagation delay and power delay product. The simulation has been carried out on a Cadence environment virtuoso tool using a 45nm,90nm,180nm Technology.

Keywords: VLSI, CMOS, Full adder, Power, Delay, Transmission gate