AXI Interface with a Multiple Master and Slave through Interconnect

Abstract: AMBA protocols are today the de facto standard for 32-bit embedded processors . The AMBA AXI protocol supports high-performance, high-frequency system designs. It is suitable for high-bandwidth and low-latency designs and provides high-frequency operation without using complex bridges. It provides flexibility in the implementation of interconnect architectures and is backward-compatible with existing AHB and APB interfaces. This Project is aimed at the Verification of the AMBA based AXI protocol has an additional write response channel to allow the slave to signal to the master the completion of the write transaction AXI protocol has an additional write response channel to allow the slave to signal to the master the completion of the write transaction. This slave interface can be used to connect different peripherals into AMBA based processors.

Keywords: Advanced   Microcontroller   Bus   Architecture (AMBA), Advanced Peripheral Bus (APB), AMBA High-performance Bus (AHB), Advanced Extensible Interface (AXI), Sysytem on Chip (SoC)