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International Journal of Advanced Research in Computer and Communication Engineering A monthly Peer-reviewed & Refereed journal
ISSN Online 2278-1021ISSN Print 2319-5940Since 2012
IJARCCE adheres to the suggestive parameters outlined by the University Grants Commission (UGC) for peer-reviewed journals, upholding high standards of research quality, ethical publishing, and academic excellence.
← Back to VOLUME 7, ISSUE 6, JUNE 2018

Compact and High Speed Hardware Implementation of CLEFIA

Pankaj V. Jadhav, Vishnu Suryawanshi

DOI: 10.17148/IJARCCE.2018.763

Abstract: Since 19th century, we were get aware of the process of communication. But, from the last 3 or 4 decades we knew how the communication is essential for entire living. It is just a process of conveying information from one end to another. One end is known as transmitter and other a receiver.  For the success of communication, there should be presence of these both. As the use of this process goes on increasing, different methods or strategies were established. Afterwards the human being experienced that, not only the communication is important but also its safety is important. To achieve safety of communication many methods are used. But, the best method while using communication is Cryptography. Clefia is one algorithm used in Cryptography. It is 128 bit block cipher algorithm. This paper presents the different work done on Clefia by different authors. Also it proposes a method for the implementation of Compact and High Speed Hardware of CLEFIA.

Keywords: Cryptographic Techniques, Encryption, Clefia, Xilinx, FPGA.

How to Cite:

[1] Pankaj V. Jadhav, Vishnu Suryawanshi, “Compact and High Speed Hardware Implementation of CLEFIA,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), DOI: 10.17148/IJARCCE.2018.763