Design and FPGA Implementation of Binary Tree Different Node Topology Network on Chip

Abstract: With the expansion in the interest for superior and fast VLSI frameworks, such as network Processors In networking or SOCs in communication and computing has shifted the focus from traditional performance Parameters towards the number of chips, LUT’s etc. and frequency consumption. Paired tree topology s the one of the topology for system on chip plan in this proposition we have effectively structure the equipment chip for bunch size 2, 4, 8 and 16 separately. The capacity on recreation is done in Modalism programming the outcomes are checked on Spartan 3EFPGA. Our binary chip is optimization in terms of hardware parameters such as LUTand flip- flop. The system supports high frequency.

Keywords: VLSI, SOCs, FPGA, LUTs.