Design and Verification of low noise and low power amplifier

Abstract: This research presents the design and verification of a low-noise, low-power amplifier (LNA) optimized for high-performance applications such as wireless communication, IoT devices, and medical sensors. The design is implemented using 45nm CMOS technology in Cadence Virtuoso to achieve an optimal balance between noise figure, power efficiency, gain, and bandwidth. The proposed LNA incorporates inductive degeneration, resistive feedback, and cascading topologies to minimize thermal noise and enhance gain. The design undergoes extensive DC, AC, noise, transient, and Monte Carlo simulations to validate robustness. Post-layout verifications, including Design Rule Check (DRC) and Layout vs. Schematic (LVS), ensure fabrication compliance. The results demonstrate a power consumption of 22.4mW, making this design suitable for energy-efficient high-frequency applications.

Keywords: Low noise and Low Power Amplifier, 45nm CMOS Technology