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DESIGN OF EMBEDDED SYSTEM OF POWER GRID SYNCHRONIZATION FAILURE DETECTION
Abstract: This ipaper ipresents ithe idesign iof ian iembedded isystem ito idetect ithe isynchronization ifailure iof iany iexternal isupply isource iwith ithe ipower igrid. iIt isenses ithe iabnormalities iin ifrequency iand ivoltage. iA iprototype ihas ibeen ideveloped iand itested, ithe iresults iin ithe iform iof ipictures iof iLCD idisplay iare ishown. For ithe iproject, irange iof ifrequency iis i48Hz ito i50Hz iand i ivoltage irange iis i200V-240V. i
How to Cite:
[1] Ronit Jain, Madhav Dogra, Ankit Mishra, Ankit Kumar, “DESIGN OF EMBEDDED SYSTEM OF POWER GRID SYNCHRONIZATION FAILURE DETECTION,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), DOI: 10.17148/IJARCCE.2022.11539