📞 +91-7667918914 | ✉️ ijarcce@gmail.com
IJARCCE Logo
International Journal of Advanced Research in Computer and Communication Engineering A monthly Peer-reviewed & Refereed journal
ISSN Online 2278-1021ISSN Print 2319-5940Since 2012
IJARCCE adheres to the suggestive parameters outlined by the University Grants Commission (UGC) for peer-reviewed journals, upholding high standards of research quality, ethical publishing, and academic excellence.
← Back to VOLUME 12, ISSUE 4, APRIL 2023

Design of Sample and Hold using 45nm Technology

Swaroop R, Sumukha P T, Dheeraj, Tanuja R, Swapna Srinivasan

DOI: 10.17148/IJARCCE.2023.12453

Abstract: The sample and hold procedure is carried out using a sample-and-hold circuit, also known as a track-and-hold circuit. It is difficult to design these circuits since they must work at the greatest signal levels and speeds. To obtain the best performance, the trade-off between noise and distortion needs to be carefully balanced. ADC is essential for many applications, including wireless communication and digital signal processing, because virtually every real-world analogue signal can be converted into a digital signal using an ADC.

Keywords: Sample and hold, track and hold, Analog-to-Digital Converter (ADC).

How to Cite:

[1] Swaroop R, Sumukha P T, Dheeraj, Tanuja R, Swapna Srinivasan, “Design of Sample and Hold using 45nm Technology,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), DOI: 10.17148/IJARCCE.2023.12453