Gate Clock Loop Pipelining of Binary Instruction Traces Power Reduced as A Review

Abstract: The increasing demand for low power mobile computing and consumer electronics products has refocused VLSI design in the last two decades on lowering power and increasing energy efficiency. Power reduction is treated at all design levels of VLSI chips. From the architecture through block and logic levels, down to gate level circuit and physical implementation, one of the major dynamic power consumers in the system clock signal, typically responsible for up to 50% of the total dynamic power consumption. Clock network design is a delicate procedure and is therefore done in a very conservative manner under worst case assumptions. It incorporates many diverse aspects such as selection of sequential elements, controlling the clock skew, the decision of the topology and physical implementation of the clock distribution network.  

Keywords: Data Driven, Logic Gates, Flip-Flops, Clock Gating, AND Clock Gating, NOR Clock Gating, Latch based Clock Gating.