A Comparative Performance Analysis of Various CMOS Design Techniques for Multiplier Circuits

Abstract: Multiplication is an important arithmetic operation that plays specific role in digital signal processing, microprocessors and scientific applications. Multipliers have become area of interest these days to search out high speed, low power consumption and area efficient multiplication algorithms. The Power- Delay product plays an effective role in overall performance of a multiplier. There are various low power digital designing techniques available to design digital multipliers. In this article various logic design techniques are used to design multipliers. As different CMOS technologies have different features, however new comparisons have been performed for efficient designing of binary multipliers. In this paper, 4-bit multipliers and 8-bit multipliers have been designed using various logic styles. The performance of both the multipliers have been compared and evaluated at different voltages on the basis of power consumption, area usage, cost applied and delay.

Keywords: CMOS, CPL, DPL, Full Adders, Logic design, Multipliers