A Fast 16×16 Vedic Multiplier Using Carry Select Adder on FPGA

Abstract: Vedic mathematics is one of the ancient Indian system of mathematics that was rediscovered in the early twentieth century This paper proposes the design of high speed Vedic Multiplier using the techniques of Vedic Mathematics that have been modified to improve performance using Carry select adders. A high speed processor depends greatly on the multiplier as it is one of the key hardware blocks in most digital signal processing systems as well as in general processors. In Vedic Mathematics calculation based on 16 sutras is a unique technique of calculations . This paper presents design and implementation of high speed 16x16 bit Vedic multiplier architecture which is quite different from the Conventional method of multiplication like addition and shifting . Further, the Verilog HDL coding of Urdhva tiryakbhyam Sutra for 16x16 bits multiplication and carry select adder is simulated and implemented on XilinxISE9.2i.

Keywords: Ripple Carry (RC) Adder, Vedic Mathematics, Vedic Multiplier (VM), Urdhava Tiryakbhyam Sutra, Carry select adder, Verilog HDL.