A Low Complexity Image Scaling Processor Using Spurious-Power Suppression Technique

Abstract: A low complexity, low memory required, high quality image scaling processor using sharpening spatial filter, clamp filter followed by bilinear interpolation is proposed. The sharpening spatial filter and clamp filter are realized by T-model and inverse T-model convolution kernel, and serves as prefilters. Furthermore to reduce memory requirement the T-model and inversed T-model kernels are combined together to form combined filter with one-line buffer memory. The proposed image scaling algorithm uses hardware sharing technique in order to reduce the computational complexity and to minimize the computing resources needed. Furthermore, Spurious-Power Suppression Technique Unit is used to overcome redundant calculation performed in Reconfigurable Calculation Unit (RCU), which reduce the computational resources and hardware cost required, which further results in reduction of gate count. Spurious-power suppression technique (SPST) adder results in reduction in power consumption and filter out the unused switching power.

Keywords: Bilinear, clamp filter, sharpening spatial filter, Spurious-Power Suppression Technique, Reconfigurable Calculation Unit.