A Novel approach of identifying uninitialized register in SOC designs

Abstract: As we know that today‟s‟SoC designs comprise of IP blocks from different design team and vendors. Integrating and verifying them is a challenge for design teams. Verification happens mainly in two stages RTL and Gate level simulation. One of the key challenges in gate level simulation of a ASIC/SoC is X (unknown) propagation debug. X propagation happens due to many reasons such as uninitialized memory, timing violations and due to non-resettable flops. X propagation due to non resettable flops are very difficult to debug and consumes enormous time, challenge further increases due to presence of hundreds/thousands of such non resettable flops which needs to be traced separately for every X propagation, To avoid these X propagation, such flops should be initialized with random value 0 or 1 in the beginning (at 0 time) to mimic silicon behavior but the problem is list of such non resettable flops is not available to the soc team and there are no efficient & reliable techniques present to identify such flops. The proposed paper explains a methodology which can generate a list of non resettable flops required to avoid „X‟ propagation in gate simulation. This uses formal tools and gate level VCD of the physical design.

Keywords: Non resettable flop, Gate level Simulation, Uninitialized register