A Robust Power Downgrading Technique using Sparse Modulo 2n+1 Adder

S.SURABHI; M.JAGADEESWARI PG Scholar; Department of VLSI Design; Sri Ramakrishna Engineering College; Coimbatore; India Professor and Head; Department of VLSI Design; Sri Ramakrishna Engineering College; Coimbatore; India &nbsp;

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A Robust Power Downgrading Technique using Sparse Modulo 2n+1 Adder

S.SURABHI, M.JAGADEESWARI PG Scholar, Department of VLSI Design, Sri Ramakrishna Engineering College, Coimbatore, India Professor and Head, Department of VLSI Design, Sri Ramakrishna Engineering College, Coimbatore, India  

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[1] S.SURABHI, M.JAGADEESWARI PG Scholar, Department of VLSI Design, Sri Ramakrishna Engineering College, Coimbatore, India Professor and Head, Department of VLSI Design, Sri Ramakrishna Engineering College, Coimbatore, India  , “A Robust Power Downgrading Technique using Sparse Modulo 2n+1 Adder,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)