Adaptive Power Reduction Technique for Adder using Multi Bit Flip Flop

Abstract: In VLSI (Very Large Scale Integration) design the power consumption is increased for more transition memory elements. Flip-flop (FF) are the basic sequential components used for memory applications. An adder and multiplier are designed using Multi-Bit Flip-Flop (MBFF). In the proposed work one of the promising ways to improve performance of FF is merging of clock pulse. Operating memory arrays with less clock cycle will reduce the power taken by the FF which leads to total power reduction and maximum internal delay can also be reduced. Besides, reducing number of FF in the circuit design the total wire length reduces the complexity of MBFF. For dynamic storage the required number of FF selected by transformation check method. Transformation check method can be effectively enabled by dynamic combinational block with check task in the proposed work.

Keywords: Power reduction, MBFF, Merging, Synthesis for low power, Wire length, Transformation check method.