Adaptive Power Reduction Technique for Adder using Multi Bit Flip Flop

[1] T.M.MINIPRIYA, M.RAMYA, T.MOHANAPRIYA, S.THILAGAVATHI, P.C.FRANKLIN PG Scholar, Embedded System Technologies, S.A Engineering College, Chennai, India Assistant Professor, Electronics and Communication Engineering Dept., S.A Engineering College, Chennai, India PG Scholar, Embedded System Technologies, S.A Engineering College, Chennai, India PG Scholar, Embedded System Technologies, S.A Engineering College, Chennai, India PG Scholar, Embedded System Technologies, S.A Engineering College, Chennai, , “Adaptive Power Reduction Technique for Adder using Multi Bit Flip Flop,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)