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An Efficient Field Programmable Gate Array Implementation Of Double Precision Floating Point Multiplier Using VHDL
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[1] SUKHVIR KAUR, PARMINDER SINGH JASSAL M.Tech Student, ECE, Yadvindra College of Engineering, Talwandi Sabo (Pb)-India Assistant Professor, ECE, Yadvindra College of Engineering, Talwandi Sabo (Pb)-India, “An Efficient Field Programmable Gate Array Implementation Of Double Precision Floating Point Multiplier Using VHDL,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)