← Back to VOLUME 2, ISSUE 11, NOVEMBER 2013
An Enhanced (15,5) BCH Decoder Using Verilog HDL
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How to Cite:
[1] M.PRASHANTHI, P.SAMUNDISWARY M. Tech, Department of Electronics Engineering, Pondicherry University, Pondicherry, India Assistant Professor, Department of Electronics Engineering, Pondicherry University, Pondicherry, India, βAn Enhanced (15,5) BCH Decoder Using Verilog HDL,β International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)
