An Enhanced (15,5) BCH Decoder Using Verilog HDL

Abstract: Error-correction codes are the codes used to correct the errors occurred during the transmission of the data in the unreliable communication mediums. The idea behind these codes is to add redundancy bits to the data being transmitted so that even if some errors occur due to noise in the channel, the data can be correctly received at the destination end. Bose, Ray- Chaudhuri, Hocquenghem (BCH)codes are one of the error-correcting codes. The BCH decoder consists of four blocks namely syndrome block, IBM block, chien search block and error correction block. This paper describes a new method for error detection in syndrome and chien search block of BCH decoder. The proposed syndrome block is used to reduce the number of computation by calculating the even number syndromes from the corresponding odd number syndromes. The new factorization method used to implement the algorithm of chien search block of enhanced BCH decoder reduces the number of components required. Thus, a new model of BCH decoder is proposed to reduce the area and simplify the computational scheduling of both syndrome and chien search blocks without parallelism leading to high throughput. The enhanced chase BCH decoder is designed using hardware description language called Verilog and synthesized in Xilinx ISE 13.2.

Keywords: BCH Codes, Syndrome Block, Chien search Block, Error detection