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Comparative Study of Adder Cells Using Different Logic Styles
LAYA SURENDRAN E K, RONY ANTONY P M.Tech Student, Department of Electronics and Communication, Rajagiri School of Engineering & Technology, Cochin, India Assistant Professor, Department of Electronics and Communication Rajagiri School of Engineering & Technology, Cochin, India
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Abstract: The main building block of many arithmetic system is the adder cells. The performance of multipliers is greatly influenced by the efficiency of the adders. Adder cells using different logic styles are discussed in this paper. Different logic styles include Cmos logic, Pass transistor logic, Transmission gates and Shannon based adders. The main aim of this work is to compare the performance of adder cells in terms of delay , power consumption, area and energy delay product. The adder cells are designed for 0.18um CMOS technology. Cadence tool is used for the simulation.
Keywords: Full adder, CMOS logic , Pass transistor logic, Transmission gate , Shannon based adder.
Keywords: Full adder, CMOS logic , Pass transistor logic, Transmission gate , Shannon based adder.
How to Cite:
[1] LAYA SURENDRAN E K, RONY ANTONY P M.Tech Student, Department of Electronics and Communication, Rajagiri School of Engineering & Technology, Cochin, India Assistant Professor, Department of Electronics and Communication Rajagiri School of Engineering & Technology, Cochin, India, βComparative Study of Adder Cells Using Different Logic Styles,β International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)
This work is licensed under a Creative Commons Attribution 4.0 International License.