Design, Analysis and FPGA Implementation of N Bit Vedic Multiplier Based on Different Adder Architectures

Abstract: The speed of the multipliers depends on the speed of the adders which are used for addition of partial products. The papers main focus is on the time delay of the multiplication operation on multipliers based on the ancient Vedic mathematical Sutra called Urdhva Tiryakbhyam i.e. vertically and cross wise Sutra. This Vedic multiplier is implemented using adder which has lesser time delay among carry look ahead adder, ripple carry adder, carry skip adder and carry select adder. The Vedic multiplier is coded in Verilog HDL and simulated using Xilinx ISE 14.3 software. This multiplier is implemented on Spartan 6 FPGA devices. The Vedic multiplier is compared in terms of time delay with conventional multiplier and it is used in Fast Fourier Transform algorithm.

Keywords: Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA), Carry Select Adder (CSA), Urdhva Tiryakbhyam, Fast Fourier Transform.