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Design and Analysis for Low power CMOS Sram cell in 90nm technology using cadence tool
SAGAR JOSHI, SARMAN HADIA PG student, Charotar University of Science & Technology, changa, India Sarman K Hadia (Associate Professor, Electronics & Communication Department, CSPIT, Changa, CHARUSAT)
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This work is licensed under a Creative Commons Attribution 4.0 International License.How to Cite:
[1] SAGAR JOSHI, SARMAN HADIA PG student, Charotar University of Science & Technology, changa, India Sarman K Hadia (Associate Professor, Electronics & Communication Department, CSPIT, Changa, CHARUSAT) , βDesign and Analysis for Low power CMOS Sram cell in 90nm technology using cadence tool,β International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)