Design and Analysis of Fundamental Gates and Adder using Adiabatic Array Logic

Abstract: Adiabatic logic uses the principle of reversible logic in order to minimize the power consumption. The reduction of power dissipation in adiabatic is achieved through the use of power clock instead of DC voltage. Adiabatic switching is mostly used to minimize the power consumption during charging and discharging. The main purpose is to design a low power circuit using adiabatic array logic which consumes less power. In this paper we have designed fundamental gates adders using adiabatic array logic and compare their power dissipation, delay and area with CMOS logic

Keywords: Adiabatic Array Logic, Complementary metal oxide semiconductor (CMOS ), Quasi adiabatic logic, Carry Select Adder (CSLA) , fundamental gates.