Design and implementation of 4-bit flash ADC using folding technique in cadence tool

S D.Panchal; Dr. S.S.Gajre; Prof. V.P.Ghanwat SGGS Institute of Engineering and Technology; Nanded; Maharashtra; India

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Design and implementation of 4-bit flash ADC using folding technique in cadence tool

S D.Panchal, Dr. S.S.Gajre, Prof. V.P.Ghanwat SGGS Institute of Engineering and Technology, Nanded, Maharashtra, India

How to Cite:

[1] S D.Panchal, Dr. S.S.Gajre, Prof. V.P.Ghanwat SGGS Institute of Engineering and Technology, Nanded, Maharashtra, India, “Design and implementation of 4-bit flash ADC using folding technique in cadence tool,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)