Design and Simulation of Wallace Tree Multiplier using Compressor

Abstract: Low power circuit designs have been an important issue in VLSI designs areas. Multipliers play a vital role in high performance systems. The Wallace Tree Multiplier is considered as faster than simple array multiplier.WTM provides a power efficient strategy for high speed multiplication. The 4-bit Wallace tree multiplier constructed by compressor based on carry bypass or carry skip adder operation. The compressor in Wallace tree multiplier reduction can further improve the speed of multiplier. The designs are implemented in TANNER EDA Tool v13.0

Keywords: WTM, Carry Skip Adder, Compressor.