Design Approach to Realise SoC to Generate Time Stamping Signal from Satellites and Updating on Ethernet for Synchronization

Abstract: The objective of this research paper is to design a �System-On-Chip (SoC)� having required modules/functional blocks in a single chip to generate accurate timing signal, derived from the satellites (GPS) signals, these are called �Timing Systems�. The timing signal is distributed over Ethernet network using protocols like Serial, IRIG, NTP etc for time stamping, time updation & to use for synchronization of systems. The satellites (GPS) signals are generally from GPS / GLONASS / GALILEO satellites constellation. The satellite signals are received and through the process of triangulation precise position of the receiver and thereby accurate time information is derived. In the absence of signals from the GPS satellites, the time updation process continues with a local clock source built with in the SoC.

Keywords: SoC, FPGA, GPS, NTP, IRIGB, Ethernet, TGL, PTP, IP Core, Acquisition, Tracking.