Design of a Low Power D-Flip Flop using AVL Technique

Abstract: Power optimization is a very crucial issue in low voltage applications. This paper presents a design of D-Flip flop circuit using AVL techniques for low power operation. It reduces the value of total power dissipation by applying the adaptive voltage level at ground (AVLG) technology in which the ground potential is raised and adaptive voltage level at supply (AVLS) in which supply potential is increased. The main aim of the design is to investigate the power dissipation for D-Flip flop for the proposed design style. The simulation results show the there is a significant reduction in power consumption for this proposed cell with the AVL technique. The AVLS technique has less power dissipation 1.3480nwatts compared to AVLG technique 2.5729nwatts. The circuit is designed using Mentor Graphics 130nm technology.

Keywords: D Flip-flop, AVL Technique, Low power, Mentor Graphics.