Design of a Modified Carry Select Adder with Single Fault Tolerant Architecture

Abstract: In the era of deep sub-micron technology, probability of chip failure has been increased with increase in chip density. A system must be fault tolerant to decrease the failure rate and increase the reliability of it. The major bases of VLSI areas are low power, high speed and data logic design. Adder forms the integral part of ALU. Different algorithm in digital signal processing such as FIR and IIR are also employed using adder. Advance result can be calculated by using possible values of input carry 0 and 1. Here carry select adder is modified with BEC and Brent kung adder. In addition triple fault tolerant architecture is implemented in the modified carry select adder. Multiple faults can affect a system simultaneously and there is a trade of between area overhead and number of faults tolerated. The proposed system models fault tolerant architecture design for modified carry select adder and a conditional sum adder as fast adder assuming single double and triple faults.

Keywords: ALU, BEC, BK.