Design of a Power Efficient Parallel Architecture for Linear Feedback Shift Registers

Abstract: This brief presents a new parallel architecture for linear feedback shift registers. This is 8-bit parallel architecture, which can be used to achieve high-throughput. In linear feedback shift registers exclusive-or is commonly used as linear function. Linear feedback shift register is determined by the feedback polynomial. Cyclic Redundancy Check (CRC) & Bose - Chaudhuri �Hocquenghem (BCH) are encoders for storage and communication systems. CRC is a system that reduces complexity of its feedback loop. When compared to previous parallel architectures based on the transposed serial LFSR. In this the LFSR based upon the IIR topology. The previous 4-bit parallel architecture has more complexity; it occupies more area, time. The proposed 8-bit parallel architecture better achieves area-time product &reduces complexity.

Keywords: Bose�Chaudhuri�Hocquenghem (BCH) encoder, cyclic redundancy check (CRC) encoder, linear feedback shift register (LFSR), parallel architecture.