Design of Efficient FIR Filter MAC unit Using Parallel Prefix Adder

Abstract: Digital Signal Processing (DSP) is a field of Utmost importance as it performs the processing of a digital signal. DSP techniques improve signal quality or extract important information by removing unwanted parts of the signal. This extraction of the unwanted parts of the signal is possible with the help of filters. A Finite Impulse Response (FIR) filters play a crucial role in many of the signal processing applications. The output is computed using Multiply and Accumulate (MAC) operations. The functionality of MAC unit enables high-speed filtering and other processing typical for DSP applications. A MAC unit consists of a multiplier and accumulator. In this paper multiplier is designed using modified Wallace multiplier and the adder used is Parallel Prefix Adder and is compared with other adders that is Carry Save Adder and Carry Select Adder. This Paper Presents Design of Low Power and High Speed MAC unit with Modified Wallace Multiplier and Parallel Prefix Adder (Kogge-Stone adder) for FIR filter. And it also gives the Comparison of three adders (Parallel Prefix Adder, Carry Save Adder, and Carry Select Adder) in Case of Power, Delay and Area. Modified Wallace multiplier with three different adders has been written Coded in VHDL and then synthesized and simulated using Xilinx ISE 9.2i. The MAC unit which designed by using Modified Wallace Multiplier and Parallel Prefix adder has consumes less Power and has less delay by when compared with other adders.

Keywords: Modified Wallace multiplier, Parallel prefix adder, Kogge-Stone adder, Carry Select adder, Carry Save adder.