Design of Energy Efficient SRAM Cell to Improve the Stability of Read Operation

Abstract: Static Random Access Memory (SRAM) is a type of Memory which is faster and more suitable than other memories such as Dynamic Random Access Memory (DRAM) or Flash Memories. The main advantage of the SRAM is need not to be refreshed. SRAM is mainly used for Cache memory in many applications such as Microprocessors, Engineering Workstations, Mainframe Computers etc�for High Speed and Low Power Consumption. The Energy Efficiency and Speed of SRAM are the most Crucial issue for minimizing the power during read and write operations. The Aim of this Paper is to provide a Energy Efficient Low Power SRAM Cell and here Technique called �Self controllable voltage level circuits� are used and various Approaches are discussed to Achieve the Better Performance. Simulation result of 9T SRAM cell with reduced power is implemented using TANNER EDA tool.

Keywords: Static Random Access Memory (SRAM), Self Controllable Voltage Level Circuit (SVL), Energy Efficiency, Leakage, Low Power.