Design of Error-Tolerant CMOS Adder Using optimized Transistor Count

Abstract: In modern VLSI technology, the occurrence of all kinds of errors cannot be avoided. So, the error-tolerant adder (ETA) is designed. Error-tolerant circuit may produce erroneous outputs but the motivation for using it is an increase in effective yield, improved revenues, and lower-cost parts. It can be seen as a new trade-off parameter besides power and speed. The three important considerations of VLSI design is power, area, and delay. Number of transistors used in adder also plays an important role in area. The proposed design of Error tolerant adder, transistor count has been reduced by incorporating the 4 transistor XOR gate in the design of Adder. When compared to other ETAs, the proposed optimized ETA is able to achieve nearly 50% improvement in the area (transistor count) with considerable power.

Keywords: VLSI, Error-Tolerant Adder (ETA), Error Tolerance (ET), Power-Delay Product (PDP).