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International Journal of Advanced Research in Computer and Communication Engineering A monthly Peer-reviewed & Refereed journal
ISSN Online 2278-1021ISSN Print 2319-5940Since 2012
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← Back to VOLUME 6, ISSUE 11, NOVEMBER 2017

Design of High-Speed and Low Power Carry Skip Adder

Pritee verma, Shiva Jaishwal, Sonam Rathora

DOI: 10.17148/IJARCCE.2017.61143

Abstract: In this paper we present high speed 8-bit Carry Skip Adder (CSA) compared with Ripple Carry Adder (RAC) and conventional Carry Skip Adder (CSA). This is more efficient in terms of power consumption, area usage and speed. Instead to make multiplexer logic, the propose architecture made of AND-OR-Inverter (AIO) combination gate for carry skip adder. The propose architecture are evaluated by comparing their speed, power and area with those of other address using 180nm, 90nm and 45nm static CMOS technology.



Keywords: Ripple Carry Adder ( RCA), Carry Skip Adder(CSKA), CI-CSKA, high performance, incrimination.

How to Cite:

[1] Pritee verma, Shiva Jaishwal, Sonam Rathora, “Design of High-Speed and Low Power Carry Skip Adder,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), DOI: 10.17148/IJARCCE.2017.61143