Design of optimized Proposed 9T SRAM Cell

Abstract: For SRAM power, stability, delay and area are the major concerns. And they are trade-offs to each other. But all are important and should be in acceptable range. In this paper we mainly concentrated on power and stability and we designed an optimized proposed 9T-SRAM for low power consumption by placing an NMOS transistor between supply voltage VDD and the latches formed by cross coupled inverters. This NMOS transistor is in diode connected mode and it scales down the VDD. So total power is reduced by 98%. Because power is directly proportional to square of VDD. But this effect the stability, as stability decreases when supply voltage decreases. In order to increase stability an extra PMOS transistor is placed in between access transistor and pull down transistor. This PMOS transistor separate�s the storage node and writing node of data. It also scales the bit line voltage and prevent the flipping the contents of cell at low voltages. So stability parameters like SINM, SVNM, WTI and WTV also increased by 93%, 45%, 86% and 56% respectively. In this proposed cell static power is also reduced by 55% due to stacking effect. This all values are when compared with Sub-threshold 10T SRAM cell. This proposed circuit is also tested by giving 0.3 V power supply. Cadence Virtuoso tools are used for simulation with gpdk-90nm CMOS process technology.

Keywords: SRAM, SINM, SVNM, WTI, WTV.