Design of Ultra Low Power 7.2 GHz True Single Phase Clock CMOS 2/3 Prescaler244 µW

Abstract: In this paper a high operating frequency and power efficient TSPC prescaler layout is proposed and compared with the existing TSPC and E-TSPC prescalers on the basis of operating frequency and power consumption. The maximum operating frequency of the proposedTSPC prescaler is 7.2 GHz which is 10% higher than other TSPC based prescalers and 7% than E-TSPC based prescalers with average power consumption of 307 �W at 1.8 V supply voltage. This High Frequency is achieved by reducing propagation delay in PMOS and NMOS at different stages. The power consumption in divide by 2 and divide by 3 mode is 3% to 10% better than all other prescalers and four times better than those prescalers which can be operated higher than 6.5 GHz frequency.This prescaler consumes 348�W in divide by 2 mode and 244�W in divide by 3 mode.

Keywords: Dual modulus prescaler, D Flip-flop (DFF), True single phase clock (TSPC), Microwind, DSCH, Frequency synthesizer, Clock, Propagation Delay.