Development of Low Power Test Data Compression Techniques for Digital VLSI Circuits

Abstract: The two noteworthy zones of worry in the testing of VLSI circuits are Test data volume and inordinate test control. Among the various pressure coding plans proposed till now, the CCSDS (Consultative Committee for Space Data Systems) lossless data pressure plan is one of the best. This paper talks about the procedures that test data pressure conspire in view of lossless data pressure Rice Algorithm as suggested by the CCSDS for the lessening of required test data add up to be put away on the analyzer, which will be exchanged amid assembling testing to every center in a system-on-a-chip (SOC). In the proposed plot, the test vectors for the SOC are compacted by utilizing Rice Algorithm, and by applying different parallel encoding methods. Exploratory results demonstrate that the test data pressure proportion for the bigger ISCAS 89 Benchmark Circuits is altogether enhanced in examination with existing techniques.

Keywords: VLSI Circuits, CCSDS, SOC, Adaptive Entropy Coder (AEC).