Effective Architecture of Packet Classification on FPGA

Abstract: For providing different quality services, router needs packet classification.Rules are frequently changing and due to multidimensional field it is difficult to maintain high speed and scalabilty in packet classification.In this work we use pipeline architecture with logic gates on FPGA.Due to use of logic gates and incorporate range search in architecture speed,memoryefficiency,power efficiency of packet classification increases as compare to any previous method used for packet classification. This method is rule set independent.

Keywords: FPGA, packet classification, pipeline architecture, router, header field.