Efficient Fault–Handling of Reconfigurable Logic in SRAM using BIST and AGT

[1] T. MOHANA PRIYA, C.SUBASHINI, T.M MINIPRIYA, S. THILAGAVATHI, R.NAGARAJAN PG Scholars, Embedded System Technologies, S.A Engineering College, Chennai, India Ph.D., Scholar, Dr MGR Educational & Research Institute University PG Scholars, Embedded System Technologies, S.A Engineering College, Chennai, India PG Scholars, Embedded System Technologies, S.A Engineering College, Chennai, India PG Scholars, Embedded System Technologies, S.A Engineering College, Chennai, India, “Efficient Fault–Handling of Reconfigurable Logic in SRAM using BIST and AGT,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)