Efficient Fault–Handling of Reconfigurable Logic in SRAM using BIST and AGT

Abstract: Fault tolerance is an important system metric for many operating environments. The conventional technique for improving system reliability is by replicating component, which uses the parameter such as cost, high design time, testing, consumption of power, volume. The proposed approach employs Adaptive group testing technique for stuck open fault and stuck short fault resolution. The Static Random Access Memory (SRAM) circuit is tested for its functionality. LFSR is used for generating the test patterns. These patterns are provided to circuit to check its functionality. A Group testing based fault resolution is incorporated into SRAM based reconfigurable Field Programmable Gate Array (FPGA) to provide an evolvable hardware system with self-organizing properties. This approach improves the performance of the system and develops new techniques for addressing BIST diagnosis method.

Keywords: SRAM, BIST, AGT, FPGA.