Energy Efficient Advanced Low Power CMOS Design to reduce power consumption in Deep Submicron Technologies in CMOS Circuit for VLSI Design

[1] AMIT SINGH GAUR, JYOTI BUDAKOTI Department of Electronics & Communication Eng., G.B.Pant Engineering College, Pauri-Garhwal, Uttarakhand India Department of Computer Science & Engineering, G.B.Pant Engineering College, Pauri-Garhwal, Uttarakhand India, “Energy Efficient Advanced Low Power CMOS Design to reduce power consumption in Deep Submicron Technologies in CMOS Circuit for VLSI Design,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)