Family of a novel 3 bit Flash ADC

Abstract: Analog –to-digital converter is an important device has a huge application in todays digitized world. Flash converter is high speed converter among all other ADCs. It consists of 2N comparators that provide thermometer coded ouput which is converted to a digital output by an encoder. In high speed ADCs comparator plays an important role for high speed application using minimization techniques. The main disadvantage of flash type ADC is power hungry so the aim is to design low power flash type ADC with low power comparator. The design issues are related to gain, phase, gain bandwidth, resolution, speed, area and power dissipation. Simple two stage opamp with miller capacitance can be used as a high gain comparator. It can be easily operated at low power. It is simulated in 180nm technology using cadence virtuoso analog design environment simulation. The op-amp uses a 1.8volt Vdd and a -1.8volt Vss and consumes a power of around 0.9mW (as per post layout simulations). The analog output of each comparator is encoded using cascading full adder designed by pass transistor logic that makes the circuit more faster.

Keywords: string of pmos load, Two stage amplifier, miller capacitance, full adders.