← Back to VOLUME 2, ISSUE 7, JULY 2013
This work is licensed under a Creative Commons Attribution 4.0 International License.
Fast Charge Pump Circuit for PLL using 50nm CMOS Technology
Downloads:
π 43 viewsπ₯ 0 downloads
How to Cite:
[1] YOGENDRA PRATAP SINGH, DR. R.K.CHAUHAN Student, Department of Electronics and Communication Engineering,Madan Mohan Malaviya Engineering College, Gorakhpur, India Asst. Professor, Department of Electronics and Communication Engineering, Madan Mohan Malaviya Engineering College, Gorakhpur, India, βFast Charge Pump Circuit for PLL using 50nm CMOS Technology,β International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)
This work is licensed under a Creative Commons Attribution 4.0 International License.