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Hard IP Core Of Memory Arbiter
KEDAR TRIVEDI, NANDISH THAKER BTech, EC, Institute of Technology, Nirma University, Ahmedabad, India BTech, EC, Institute of Technology, Nirma University, Ahmedabad, India
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Abstract: This paper deals with the design of 4X4 memory arbiter and its results. The memory arbiter is completely optimized from synthesis till VLSI layout design. The designed block of 4X4 arbiter can be re used as a component to have N number of clients. Memory arbiter is an important system for controlling multiple requests. It works according to the priority of the request.
Keywords: arbiter, priority encoder, round robin, vlsi technology
Keywords: arbiter, priority encoder, round robin, vlsi technology
How to Cite:
[1] KEDAR TRIVEDI, NANDISH THAKER BTech, EC, Institute of Technology, Nirma University, Ahmedabad, India BTech, EC, Institute of Technology, Nirma University, Ahmedabad, India , βHard IP Core Of Memory Arbiter,β International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)
This work is licensed under a Creative Commons Attribution 4.0 International License.