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This work is licensed under a Creative Commons Attribution 4.0 International License.
High Speed Double Precision Floating Point Multiplier
Addanki Purna Ramesh, Rajesh Pattimi
Department of ECE, Sri Vasavi Engineering College, Pedatadepalli, Tadepalligudem, India
Abstract: In this paper we describe an implementation of high speed IEEE 754 double precision floating point multiplier targeted for Xilinx Virtex-6 FPGA. Verilog is used to implement the design. The multiplier implement area optimized design, high speed operation with latency of seven clock cycles, it handles the overflow, underflow cases, and the multiplier support truncation rounding mode was implemented. The multiplier was verified against Xilinx floating point multiplier core.
Keywords: binary floating point, multiplication, FPGA.
Keywords: binary floating point, multiplication, FPGA.
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This work is licensed under a Creative Commons Attribution 4.0 International License.How to Cite:
[1] Addanki Purna Ramesh, Rajesh Pattimi, “High Speed Double Precision Floating Point Multiplier,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)