Low Power and High Speed Multiplier Designs using FinFET Technology

Abstract: The preference to optimize the layout metrics of overall performance, strength, area, fee, and time to market (opportunity cost) has now not changed for the reason that inception of the IC enterprise. In truth, Moore�s law is all about optimizing those parameters. however, as scaling of producing nodes progressed in the direction of 20-nm, some of the tool parameters couldn't be scaled any in addition, specifically the strength deliver voltage, the dominant component in figuring out dynamic electricity. This research is to lessen the strength and put off at the FinFET based array multiplier. The backend device synopsys HSPICE is selected for the analysis of power dissipation and put off of multiplier. in this paper, four- enter multiplier is designed and simulated in 32 nm era the usage of FinFET technology. Simulation end result imply that the proposed technique offer improvement in term of strength consumption and delay over MOSFET.

Keywords: FinFET, Average Power, Multiplier